Development of 3D P in Si quantum computing architecture for error correction

Mr Mitchell Kiczynski
4pm Thursday 19 April 2018
CQC2T Conference Room, Level 2, Newton Building J12, UNSW Kensington Campus

Phosphorus donor devices in silicon fabricated using STM hydrogen resist lithography are typically fabricated in a 2D design using a single lithographic layer. However in order to achieve quantum error correction with a surface code architecture we need to be able to fabricate devices in three dimensions using multiple lithographic layers [1]. Here I will present on the fabrication challenges associated with transitioning from single layer devices to a multilayer structure and the techniques we used to overcome these challenges, allowing for the fabrication of high quality multilayer devices. I will also present electrical measurements from initial three layer vertical SET devices, the smallest element of the proposed surface code architecture [1], in which the SET source, island and drain are all separated vertically across three lithographic layers.

[1] Hill et al, Science Advances, 1, 9, e1500707 (2015)